As shown in FIG. 1, a conventional synchronous buck-boost power converter 10 includes a buck-boost power stage 12, and a control circuit 14 to provide control signals VA, VB, VC and VD t6 switch the power switches SWA, SWB, SWC and SWD in the buck-boost power stage 12, respectively, to convert an input voltage Vin to an output voltage Vo. In the control circuit 14, resistors R1 and R2 establish a voltage divider to divide the output voltage Vo to generate a feedback signal VFB, an error amplifier 24 amplifies the difference between the feedback signal VFB and a reference voltage Vref to generate an error signal VCL, a signal generator 22 provides a signal VU related to the error signal VCL and ramp signals VX and VY, a comparator 18 compares the signal VU with the ramp signal VX to generate a signal VZ1, a comparator 20 compares the signal VU with the ramp signal VY to generate a signal VZ2, and a drive logic circuitry 16 generates the control signals VA, VB, VC and VD according to the signals VZ1 and VZ2.
FIG. 2 is a waveform diagram of the buck-boost power converter 10 shown in FIG. 1, in which waveform 26 represents the ramp signal VY, waveform 28 represents the signal VU, waveform 30 represents the ramp signal VX, waveform 32 represents the signal VZ1, waveform 34 represents the signal VZ2, waveform 36 represents the control signal VA, waveform 38 represents the control signal VB, waveform 40 represents the control signal VC, and waveform 42 represents the control signal VD. Referring to FIGS. 1 and 2, as shown by the waveforms 28, 30 and 32, when the ramp signal VX is higher than the signal VU, e.g., from time t1 to time t2, the signal VZ1 is low, and when the ramp signal VX is lower than the signal VU, e.g., from time t2 to time t5, the signal VZ1 is high. As shown by the waveforms 26, 28 and 34, when the ramp signal VY is higher than the signal VU, e.g., from time t0 to time t3, the signal VZ2 is low, and when the ramp signal VY is lower than the signal VU, e.g., from time t3 to time t4, the signal VZ2 is high. The duration of time t1 to time t5 is a cycle of the output voltage Vo. From time t1 to time t2, the buck-boost power stage 12 is in a first state, during which the power switches SWA and SWC are off and the power switches SWB and SWD are on, as shown by the waveforms 36 to 42. From time t2 to time t3, the buck-boost power stage 12 is in a second state, during which the power switches SWA and SWD are on and the power switches SWB and SWC are off. From time t3 to time t4, the buck-boost power stage 12 is in a third state, during which the power switches SWA and SWC are on and the power switches SWB and SWD are off. From time t4 to time t5, the buck-boost power stage 12 is also in the second state. Thus the second state appears twice in a cycle. If the switching sequence of the power switches SWA, SWB, SWC and SWD can be changed such that the two time periods of the second state in a cycle are arranged next to each other, then the switching loss can be minimized and thereby the efficiency is improved. Furthermore, when the signal VU increases to be close to a peak of the ramp signal VX or decreases to be close to a valley of the ramp signal VY, the control signal VB or VC will have a very short duty and thereby the power switch SWB or SWC will be turned off before being turned on completely, which is meaningless apart from increasing the switching loss.
U.S. Pat. No. 7,176,667 teaches to switch the power switches SWA, SWB, SWC and SWD in a buck-boost mode according to a pulse-width modulation (PWM) signal having a modulated pulse width varying with the output voltage Vo and a signal having a fixed pulse width to insert a fixed duty in each cycle. However, this fixed duty inserted method may cause a discontinuous duty during mode switching and thereby result in large output ripple.
Therefore, it is desired a control circuit and method for optimized switching sequence of the power switches, improved efficiency, and minimized output ripple whenever mode transient.